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Yogesh Singh Chauhan
PhD (Ecole Polytechnique Federale de Lausanne (EPFL), Switzerland)
Professor, Departement of Electrical Engineering
Research Interest
Nanoelectronics Compact modeling of semiconductor devices (Bulk/SOI MOSFET, Multigate FET, Nanowire, UTBSOI and novel devices) SPICE Modelling of High Voltage/Power Semiconductor Devices (LDMOS, VDMOS, IGBT, HEMT etc.) BSIM model development and support (with BSIM Group at University of California Berkeley) Atommistic Simulation of Nanoscale Devices
DC, CV and RF Characterization
Office
WL125
Department of Electrical Engineering
Indian Institute of Technology
Kanpur, U.P. - 208016
Labs addresses: Nanolab (WL215)
Specialization
Compact Modeling
Education
PhD, Ecole Polytechnique Federale de Lausanne (EPFL), Switzerland ‐ 2004‐2007Thesis Title:Compact modeling of high voltage MOSFETsThesis Supervisor:Adrian M. Ionscue
M.Tech, Indian Institute of Technology, Kanpur 2001‐ 2003
B. Tech, S G S I T S Indore – 1997‐2001
Teaching Area
EE698L (Compact Modeling)
EE614 (Solid State Devices - I)
EE370 tutorial (Digital Electronics and Microprocessor Technology)
EE210 tutorial (Microelectronics - I)
ESC201A tutorial and lab (Introduction to Electronics)
Professional Affiliations
Editor of Institution of Electronics and Telecommunication Engineers (IETE) Technical Review
Senior Member of IEEE
Selected Publications
Y. S. Chauhan, S. Venugopalan, M.-A. Chalkiadaki, M. A. Karim, H. Agarwal, S. Khandelwal, N. Paydavosi, J. P. Duarte, C. C. Enz, A. M. Niknejad, and C. Hu, "BSIM6: Analog and RF Compact Model for Bulk MOSFET," IEEE Transactions on Electron Devices, Vol. 61, Issue 2, Feb. 2014.
Y. S. Chauhan, C. Anghel, F. Krummenacher, C. Maier, R. Gillon, B. Bakeroot, B. Desoete, S. Frere, A. Baguenier Desormeaux, A. Sharma, M. Declercq, and A. M. Ionescu, "Scalable General High Voltage MOSFET Model including Quasi-Saturation and Self- Heating effect," Solid State Electronics, Vol. 50, Issues 11-12, pp. 1801-1813, Nov.-Dec. 2006.
S. Khandelwal, C.Yadav, S. Agnihotri, Y. S. Chauhan, A. Curutchet, T. Zimmer, J.-C. Dejaeger, N. Defrance, and T. A. Fjeldly, "A Robust Surface-Potential-Based Compact Model for GaN HEMT IC Design," IEEE Transactions on Electron Devices, Vol. 60, Issue 10, Oct. 2013.
Y. S. Chauhan, D. Tsamados, N. Abele, C. Eggimann, M. Declercq, and A. M. Ionescu, "Compact Modeling of Suspended Gate FET," IEEE International Conference on VLSI Design, Hyderabad, India, Jan. 2008.
Y. S. Chauhan, F. Krummenacher, C. Anghel, R. Gillon, B. Bakeroot, M. Declercq, and A. M. Ionescu, "Analysis and Modeling of Lateral Non-Uniform Doping in High-Voltage MOSFETs," IEEE International Electron Devices Meeting, San Francisco, USA, Dec. 2006.
Awards & Fellowships
Received IBM Faculty Award (2013)
Awarded Ramanujan Fellowship by Department of Science and Technology (2012)
Senior Member of IEEE
Honorable Mention Award in IEEE VLSI conference - Jan 2008
Keywords
Compact Model, SPICE, BSIM-CMG, BSIM-IMG, BSIM6, HEMT Model
Professional Experience
2010-2012 - University of California Berkeley
2010 - Tokyo Institutre of Technology, Tokyo, Japan
2007-2010 - IBM Bangalore
2003-2004 - ST Microelectronics